Automatic Generation of Microarchitecture Simulators

In this paper we describe the UPFAST system that automatically generates a cycle level simulator, an assembler and a disassembler from a microarchitec-ture speciication written in a domain speciic language called the Architecture Description Language (ADL). Using the UPFAST system it is easy to retarget a sim-ulator for an existing architecture to a modiied architecture since one has to simply modify the input spec-iication and the new simulator is generated automatically. UPFAST also allows porting of simulators to diierent platforms with minimal eeort. We have been able to develop three simulators ranging from simple pipelined processors to complicated out-of-order issue processors over a short period of three months. While the speciications of the architectures varied from 5000 to 6000 lines of ADL code, the sizes of automatically generated software varied from 20,000 to 30,000 lines of C++ code. The automatically generated simulators are less than 2 times slower than hand coded simula-tors for similar architectures.